1. Field of the Invention
This invention is related to the field of microprocessors, and more particularly, the handling of flag values during the speculative execution of instructions.
2. Description of the Related Art
High performance microprocessors use various techniques to speed up the execution of instructions, including the speculative/out-of-order execution of instructions. Since speculatively executed instructions may update the registers in a microprocessor, a means for storing speculative results that may be written to the logical (architected) registers may be implemented.
Register renaming is a technique used to keep track of speculative results that may be intended to be written to the logical registers. A microprocessor employing register renaming may include a physical register file which may store several copies of results intended for the logical registers. Each logical register may be associated with speculative results stored in a number of physical registers, as well as one non-speculative result stored in a physical register. This may allow several speculative results to be stored for each logical register, and may further allow for instructions to be executed out of order without concern for overwriting various results before they are no longer needed.
Although register renaming may allow instructions to be executed out of order without overwriting older register results, other hazards may be present. One such hazard involves the flag bits (e.g., carry, overflow, etc.). Some instructions, when executed, may update both the logical register results and one or more of the flag bits, while other instructions may update logical register results without updating flag bits.
In some cases, an instruction may be executed which updates both a logical register and a flag value, followed by the execution of a subsequent instruction which updates the same logical register without any corresponding updates of the flag values. Only the most recent value of the logical register may be considered valid, while the previous value may be considered dead, or invalid. However, the flag values, which were updated with the previous instruction (associated with the now-dead register value) may still be valid since the most recent instruction did not update the flag values. Thus, any future references to the flags shall receive the flags generated by executing the previous instruction. If the same physical register stores both a logical register value and a flags value, the above situation may complicate the freeing of physical registers in the register renaming mechanism.